ghc-9.12: The GHC API
Safe HaskellNone
LanguageGHC2021

GHC.CmmToAsm.AArch64.Instr

Synopsis

Documentation

stackFrameHeaderSize :: Int Source #

LR and FP (8 byte each) are the prologue of each stack frame

spillSlotSize :: Int Source #

All registers are 8 byte wide.

stackAlign :: Int Source #

The number of bytes that the stack pointer should be aligned to.

maxSpillSlots :: NCGConfig -> Int Source #

The number of spill slots available without allocating more.

spillSlotToOffset :: NCGConfig -> Int -> Int Source #

Convert a spill slot number to a *byte* offset, with no sign.

callerSavedRegisters :: [Reg] Source #

0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | |== General Purpose registers ==================================================================================================================================| | argument passing ------------- | IR | tmp registers -------- | IP0| IP1| PL | callee saved ------------ | FP | LR | SP | | free registers -------------------------------------------------------------------- | BR | Sp | Hp | R1 | R2 | R3 | R4 | R5 | R6 | SL | -- | -- | -- | |== SIMD/FP Registers ==========================================================================================================================================| | argument passing ------------- | callee saved (lower 64 bits) --- | caller saved ---------------------- | | free registers ------------- | F1 | F2 | F3 | F4 | D1 | D2 | D3 | D4 | free registers ----------------------------------------------------- | '---------------------------------------------------------------------------------------------------------------------------------------------------------------' IR: Indirect result location register, IP: Intra-procedure register, PL: Platform register, FP: Frame pointer, LR: Link register, SP: Stack pointer BR: Base, SL: SpLim

TODO: The zero register is currently mapped to -1 but should get it's own separate number.

patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr Source #

Apply a given mapping to all the register references in this instruction.

isJumpishInstr :: Instr -> Bool Source #

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

jumpDestsOfInstr :: Instr -> [BlockId] Source #

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr Source #

Change the destination of this jump instruction. Used in the linear allocator when adding fixup blocks for join points.

mkSpillInstr :: HasCallStack => NCGConfig -> RegWithFormat -> Int -> Int -> [Instr] Source #

An instruction to spill a register into a spill slot.

takeDeltaInstr :: Instr -> Maybe Int Source #

See if this instruction is telling us the current C stack delta

mkRegRegMoveInstr :: Format -> Reg -> Reg -> Instr Source #

Copy the value in a register to another one. Must work for all register classes.

takeRegRegMoveInstr :: Instr -> Maybe (Reg, Reg) Source #

Take the source and destination registers from a move instruction of same register class (RegClass).

The idea is to identify moves that can be eliminated by the register allocator: If the source register serves no special purpose, one could continue using it; saving one move instruction. For this, the register kinds (classes) must be the same (no conversion involved.)

mkJumpInstr :: BlockId -> [Instr] Source #

Make an unconditional jump instruction.

data Instr Source #

Constructors

COMMENT SDoc 
MULTILINE_COMMENT SDoc 
ANN SDoc Instr 
LOCATION Int Int Int String 
NEWBLOCK BlockId 
DELTA Int 
SXTB Operand Operand 
UXTB Operand Operand 
SXTH Operand Operand 
UXTH Operand Operand 
PUSH_STACK_FRAME

SXTW Operand Operand | SXTX Operand Operand

POP_STACK_FRAME 
ADD Operand Operand Operand

ADC Operand Operand Operand -- rd = rn + rm + C | ADCS ...

CMP Operand Operand

ADDS Operand Operand Operand -- rd = rn + rm | ADR ... | ADRP ...

CMN Operand Operand 
MSUB Operand Operand Operand Operand

MADD ... | MNEG ...

MUL Operand Operand Operand 
NEG Operand Operand 
SDIV Operand Operand Operand

NEGS ... | NGC ... | NGCS ... | SBC ... | SBCS ...

SMULH Operand Operand Operand

SMADDL ... | SMNEGL ... | SMSUBL ...

SMULL Operand Operand Operand 
SUB Operand Operand Operand 
UDIV Operand Operand Operand

SUBS ...

UMULH Operand Operand Operand

UMADDL ... -- Xd = Xa + Wn × Wm | UMNEGL ... -- Xd = - Wn × Wm | UMSUBL ... -- Xd = Xa - Wn × Wm

UMULL Operand Operand Operand 
SBFM Operand Operand Operand Operand 
UBFM Operand Operand Operand Operand 
SBFX Operand Operand Operand Operand 
UBFX Operand Operand Operand Operand 
CLZ Operand Operand 
RBIT Operand Operand 
REV Operand Operand 
REV16 Operand Operand 
AND Operand Operand Operand

REV32 Operand Operand -- rd = reverseBytes32(rn) - 64bit operands only! -- 0xAABBCCDD_EEFFGGHH -> 0XDDCCBBAA_HHGGFFEE

ASR Operand Operand Operand 
EOR Operand Operand Operand 
LSL Operand Operand Operand 
LSR Operand Operand Operand 
MOV Operand Operand 
MOVK Operand Operand 
MOVZ Operand Operand

MOVN Operand Operand

MVN Operand Operand 
ORR Operand Operand Operand 
STR Format Operand Operand 
STLR Format Operand Operand 
LDR Format Operand Operand 
LDAR Format Operand Operand 
CSET Operand Cond 
CBZ Operand Target 
CBNZ Operand Target 
J Target 
B Target 
BL Target [Reg] 
BCOND Cond Target 
DMBISH DMBISHFlags 
FMOV Operand Operand 
FCVT Operand Operand 
SCVTF Operand Operand 
FCVTZS Operand Operand 
FABS Operand Operand 
FMIN Operand Operand Operand 
FMAX Operand Operand Operand 
FSQRT Operand Operand 
FMA FMASign Operand Operand Operand Operand

Floating-point fused multiply-add instructions

  • fmadd : d = r1 * r2 + r3
  • fnmsub: d = r1 * r2 - r3
  • fmsub : d = - r1 * r2 + r3
  • fnmadd: d = - r1 * r2 - r3

data DMBISHFlags Source #

Constructors

DmbLoad 
DmbLoadStore 

Instances

Instances details
Show DMBISHFlags Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Eq DMBISHFlags Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

data Target Source #

Instances

Instances details
Eq Target Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: Target -> Target -> Bool #

(/=) :: Target -> Target -> Bool #

Ord Target Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

data ExtMode Source #

Constructors

EUXTB 
EUXTH 
EUXTW 
EUXTX 
ESXTB 
ESXTH 
ESXTW 
ESXTX 

Instances

Instances details
Show ExtMode Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Eq ExtMode Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: ExtMode -> ExtMode -> Bool #

(/=) :: ExtMode -> ExtMode -> Bool #

data ShiftMode Source #

Constructors

SLSL 
SLSR 
SASR 
SROR 

Instances

Instances details
Show ShiftMode Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Eq ShiftMode Source # 
Instance details

Defined in GHC.CmmToAsm.AArch64.Instr

Orphan instances

Outputable RegUsage Source #

Get the registers that are being used by this instruction. regUsage doesn't need to do any trickery for jumps and such. Just state precisely the regs read and written by that insn. The consequences of control flow transfers, as far as register allocation goes, are taken care of by the register allocator.

RegUsage = RU [regs] [regs]

Instance details

Methods

ppr :: RegUsage -> SDoc Source #