Debugging Makefiles is something of a black art, but here's a couple of tricks that we find particularly useful. The following command allows you to see the contents of any make variable in the context of the current Makefile:

$ make show VALUE=HS_SRCS

where you can replace HS_SRCS with the name of any variable you wish to see the value of.

GNU make has a -d option which generates a dump of the decision procedure used to arrive at a conclusion about which files should be recompiled. Sometimes useful for tracking down problems with superfluous or missing recompilations.

To get started, let us look at the Makefile for an imaginary small fptools project, small. Each project in fptools has its own directory in FPTOOLS_TOP, so the small project will have its own directory FPOOLS_TOP/small/. Inside the small/ directory there will be a Makefile, looking something like this:

# Makefile for fptools project "small"

TOP = ..
include $(TOP)/mk/boilerplate.mk

SRCS = $(wildcard *.lhs) $(wildcard *.c)
HS_PROG = small

include $(TOP)/target.mk

this Makefile has three sections:

In our example Makefile, most of the work is done by the two included files. When you say gmake all, the following things happen:

All Makefiles should follow the above three-section format.

Larger projects are usually structured into a number of sub-directories, each of which has its own Makefile. (In very large projects, this sub-structure might be iterated recursively, though that is rare.) To give you the idea, here's part of the directory structure for the (rather large) GHC project:

$(FPTOOLS_TOP)/ghc/
  Makefile
  mk/
    boilerplate.mk
    rules.mk
   docs/
    Makefile
    ...source files for documentation...
   driver/
    Makefile
    ...source files for driver...
   compiler/
    Makefile
    parser/...source files for parser...
    renamer/...source files for renamer...
    ...etc...

The sub-directories docs, driver, compiler, and so on, each contains a sub-component of GHC, and each has its own Makefile. There must also be a Makefile in $(FPTOOLS_TOP)/ghc. It does most of its work by recursively invoking gmake on the Makefiles in the sub-directories. We say that ghc/Makefile is a non-leaf Makefile, because it does little except organise its children, while the Makefiles in the sub-directories are all leaf Makefiles. (In principle the sub-directories might themselves contain a non-leaf Makefile and several sub-sub-directories, but that does not happen in GHC.)

The Makefile in ghc/compiler is considered a leaf Makefile even though the ghc/compiler has sub-directories, because these sub-directories do not themselves have Makefiles in them. They are just used to structure the collection of modules that make up GHC, but all are managed by the single Makefile in ghc/compiler.

You will notice that ghc/ also contains a directory ghc/mk/. It contains GHC-specific Makefile boilerplate code. More precisely:

So these two files are the place to look for GHC-wide customisation of the standard boilerplate.

Every Makefile includes a boilerplate.mk file at the top, and target.mk file at the bottom. In this section we discuss what is in these files, and why there have to be two of them. In general:

If you look at $(FPTOOLS_TOP)/mk/boilerplate.mk you will find that it consists of the following sections, each held in a separate file:

Any of the variables and pattern rules defined by the boilerplate file can easily be overridden in any particular Makefile, because the boilerplate include comes first. Definitions after this include directive simply override the default ones in boilerplate.mk.

There are three platforms of interest when building GHC:

These platforms are set when running the configure script, using the --build, --host, and --target options. The mk/config.mk file defines several symbols related to the platform settings (see mk/config.mk for details).

We don't currently support build & host being different, because the build process creates binaries that are both run during the build, and also installed.

If host and target are different, then we are building a cross-compiler. For GHC, this means a compiler which will generate intermediate .hc files to port to the target architecture for bootstrapping. The libraries and stage 2 compiler will be built as HC files for the target system (see Section 10, “Porting GHC” for details.

More details on when to use BUILD, HOST or TARGET can be found in the comments in config.mk.

The file suffix.mk defines standard pattern rules that say how to build one kind of file from another, for example, how to build a .o file from a .c file. (GNU make's pattern rules are more powerful and easier to use than Unix make's suffix rules.)

Almost all the rules look something like this:

%.o : %.c
      $(RM) $@
      $(CC) $(CC_OPTS) -c $< -o $@

Here's how to understand the rule. It says that something.o (say Foo.o) can be built from something.c (Foo.c), by invoking the C compiler (path name held in $(CC)), passing to it the options $(CC_OPTS) and the rule's dependent file of the rule $< (Foo.c in this case), and putting the result in the rule's target $@ (Foo.o in this case).

Every program is held in a make variable defined in mk/config.mk—look in mk/config.mk for the complete list. One important one is the Haskell compiler, which is called $(HC).

Every program's options are are held in a make variables called <prog>_OPTS. the <prog>_OPTS variables are defined in mk/opts.mk. Almost all of them are defined like this:

CC_OPTS = \
  $(SRC_CC_OPTS) $(WAY$(_way)_CC_OPTS) $($*_CC_OPTS) $(EXTRA_CC_OPTS)

The four variables from which CC_OPTS is built have the following meaning:

target.mk contains canned rules for all the standard targets described in Section 7.7, “Standard Targets”. It is complicated by the fact that you don't want all of these rules to be active in every Makefile. Rather than have a plethora of tiny files which you can include selectively, there is a single file, target.mk, which selectively includes rules based on whether you have defined certain variables in your Makefile. This section explains what rules you get, what variables control them, and what the rules do. Hopefully, you will also get enough of an idea of what is supposed to happen that you can read and understand any weird special cases yourself.

All of these rules are “double-colon” rules, thus

install :: $(HS_PROG)
      ...how to install it...

GNU make treats double-colon rules as separate entities. If there are several double-colon rules for the same target it takes each in turn and fires it if its dependencies say to do so. This means that you can, for example, define both HS_PROG and LIBRARY, which will generate two rules for install. When you type gmake install both rules will be fired, and both the program and the library will be installed, just as you wanted.

In leaf Makefiles the variable SUBDIRS is undefined. In non-leaf Makefiles, SUBDIRS is set to the list of sub-directories that contain subordinate Makefiles. It is up to you to set SUBDIRS in the Makefile. There is no automation here—SUBDIRS is too important to automate.

When SUBDIRS is defined, target.mk includes a rather neat rule for the standard targets (Section 7.7, “Standard Targets” that simply invokes make recursively in each of the sub-directories.

These recursive invocations are guaranteed to occur in the order in which the list of directories is specified in SUBDIRS. This guarantee can be important. For example, when you say gmake boot it can be important that the recursive invocation of make boot is done in one sub-directory (the include files, say) before another (the source files). Generally, put the most independent sub-directory first, and the most dependent last.

We sometimes want to build essentially the same system in several different “ways”. For example, we want to build GHC's Prelude libraries with and without profiling, so that there is an appropriately-built library archive to link with when the user compiles his program. It would be possible to have a completely separate build tree for each such “way”, but it would be horribly bureaucratic, especially since often only parts of the build tree need to be constructed in multiple ways.

Instead, the target.mk contains some clever magic to allow you to build several versions of a system; and to control locally how many versions are built and how they differ. This section explains the magic.

The files for a particular way are distinguished by munging the suffix. The “normal way” is always built, and its files have the standard suffices .o, .hi, and so on. In addition, you can build one or more extra ways, each distinguished by a way tag. The object files and interface files for one of these extra ways are distinguished by their suffix. For example, way mp has files .mp_o and .mp_hi. Library archives have their way tag the other side of the dot, for boring reasons; thus, libHS_mp.a.

A make variable called way holds the current way tag. way is only ever set on the command line of gmake (usually in a recursive invocation of gmake by the system). It is never set inside a Makefile. So it is a global constant for any one invocation of gmake. Two other make variables, way_ and _way are immediately derived from $(way) and never altered. If way is not set, then neither are way_ and _way, and the invocation of make will build the “normal way”. If way is set, then the other two variables are set in sympathy. For example, if $(way) is “mp”, then way_ is set to “mp_” and _way is set to “_mp”. These three variables are then used when constructing file names.

So how does make ever get recursively invoked with way set? There are two ways in which this happens:

Sometimes the canned rule just doesn't do the right thing. For example, in the nofib suite we want the link step to print out timing information. The thing to do here is not to define HS_PROG or C_PROG, and instead define a special purpose rule in your own Makefile. By using different variable names you will avoid the canned rules being included, and conflicting with yours.